Conductive spacers extended floating gates

ABSTRACT

A method for manufacturing on a substrate ( 24 ) a semiconductor device with improved floating-gate to control-gate coupling ratio is described. The method comprises the steps of first forming an isolation zone ( 22 ) in the substrate ( 24 ), thereafter forming the floating gate ( 28 ) on the substrate ( 24 ), thereafter extending the floating gate ( 28 ) using polysilicon spacers ( 40 ), and thereafter forming the control gate ( 44 ) over the floating gate ( 28 ) and the polysilicon spacers ( 40 ). Such a semiconductor device may be used in flash memory cells or EEPROMs.

The present invention relates to a method for forming a floating gate(FG) extended with conductive spacers, usable for manufacturing of ultrahigh density non-volatile memories (NVM) as well as semiconductordevices using the extended floating gate. Some examples of NVMs includean EPROM, an EEPROM and a flash memory cell.

NVMs are used in a wide variety of commercial and military electronicdevices and equipment, such as e.g. hand-held telephones, radios anddigital cameras. The market for these electronic devices continues todemand devices with a lower voltage, lower power consumption and adecreased chip size.

Flash memories or flash memory cells comprise a MOSFET with a (or aplurality of) floating gate(s) between a control gate and a channelregion, the floating gate(s) and the control gate being separated by athin dielectric layer. With the improvement of fabrication technologies,the floating gate size and the space between floating gates has beenreduced to sub-micrometer scale. These devices are basically miniatureEEPROM cells in which electrons (or holes) are injected through an oxidebarrier in a floating gate. Charges stored in the floating gate modifythe device threshold voltage. In this way, data is stored. The controlgate controls the floating gate. The floating-gate to control-gatecoupling ratio, which is related to the areal overlap between thefloating gate and the control gate, affects the read/write speed of theflash memory. Furthermore, the better the coupling ratio, the more therequired operation voltage of the memory cell can be reduced.

Stacked gate technology is applied in the fabrication of modernnon-volatile memory (NVM) cells with very high density, as shown inFIG. 1. In a stacked gate technology, the control gate (CG) 2 and thefloating gate (FG) 4 are etched in a self-aligned manner in one and thesame patterning step, resulting in zero overlap of the CG 2 over the FG4 in the direction of the active area 6. This is shown in FIG. 2, whichis a cross-section in the direction X-X′ of one of the NVM cellsrepresented in FIG. 1. FIG. 3 shows a cross-section in the directionY-Y′ of the NVM cell represented in FIG. 1. It is shown that FGs 4 arelocated apart from each other to assure isolation of the FGs 4 in theY-Y′ direction. This is achieved by etching FG slits 8 in the bottompolysilicon gate prior to depositing an interpoly dielectric (IPD) 10and a CG polysilicon layer 12. The slits 8 can either be continuouslines or separated small slits. In both cases fence leakage occurs: withcontinuous slit lines, leakage is observed between FGs in the X-X′direction, and with separated slits, leakage is observed between FGs inthe X-X′ direction and in the Y-Y′ direction.

The contribution of the potential on the CG, V_(CG), to the potential onthe FG, V_(FG), in a non-volatile memory (NVM) cell, is determined bythe FG to CG coupling ratio, α_(FC):V _(FG)=α_(FC) ×V _(CG)The FG to CG coupling ratio is determined by:α_(FC) =C _(FC) /C _(tot)where C_(FC) if the capacitance between FG and CG, and

C_(tot) is the total capacitance of the FG.

In order to achieve maximum FG to CG coupling, the capacitance C_(FC)between FG and CG must be maximized, and/or the total capacitance of theFG must be minimized.

One solution for improving the floating gate to control gate couplingratio is to increase the dimensions of the floating gate, thusincreasing the overlap area of the CG over the FG in the Y-Y′ directionas in FIG. 1 a, so as to increase the capacitance C_(FC). This, however,limits the ability to reduce the cell size and thus impedes devicedensity improvements. Maximum density requires minimum spaces betweenFGs, or thus minimum slits 8. Slit dimensions are limited bylithographic processes used in manufacturing the gate stacks.

It is known from U.S. Pat. No. 6,214,667 to make small slits by usingnitride (Si₃N₄) spacers. In this technique, slits are etched in a(relative thick) nitride layer on top of the FGs. Next, nitride sidewallspacers are formed. The nitride layer including spacers functions as ahard mask for the FG slit etch. A disadvantage of this method is theremoval of the nitride, for example with H₃PO₄ phosphoric acid thatetches (especially doped) polysilicon. This requires a trade-off betweenleaving behind nitride residues and causing a rough FG surface. Bothsituations will lead to IPD reliability problems. Furthermore, sharp FGedges are obtained, reducing the IPD reliability still more.

Another method is basically used to prevent poor tunnel oxide edges.U.S. Pat. No. 6,130,129 describes how to increase the FG to CG couplingratio by reducing the total FG capacitance. In this document this isachieved by applying self-aligned FGs revealing only a small overlap ofthe FG over the active area/substrate. This is done by etching trenchesin the substrate self-aligned with the FGs. The trenches are filled upwith an isolating oxide. This oxide reaches above the substrate surfacecovering a part of the FG polysilicon sidewalls. This causes some lossin the FG to CG capacitance. The spacers formed in U.S. Pat. No.6,130,129 have only a limited height, reducing the FG to CG capacitance.When applied in a stacked gate technology, preventing fence leakage isdifficult for these low spacers, as they contain only a minor part thatis straight in a direction perpendicular to the substrate. Furthermore,the processing described is rather complex and difficult to embed inlogic CMOS processes.

It is an object of the present invention to provide a method of forminga spacer-extended FG with an improved (higher) FG to CG coupling ratio,which is reliable and can be embedded in logic CMOS processes.

It is a further object of the present invention to provide asemiconductor device having a spacer-extended FG with an improved(higher) FG to CG coupling ratio, which is reliable and can be embeddedin logic CMOS processes.

The present invention describes a conductive spacer-extended FGmanufacturing method and device that offers the possibility to scale NVMcells towards deep sub-micron dimensions, while maintaining highreliability and FG to CG coupling.

The present invention provides a method for manufacturing on a substratea semiconductor device with a floating gate (FG) and a control gate(CG). The method comprises the steps of: first forming isolation zonesin the substrate, thereafter forming a floating gate on the substratebetween two isolation zones, thereafter extending the floating gateusing conductive spacers, and thereafter forming a control gate over thefloating gate and the conductive spacers. The isolation zones may beshallow trench isolation (STI) zones, or locally oxidized semiconductor(LOCOS) regions.

With the method of the present invention, the overlapping area betweenthe FG and the CG is increased without increase in the cell size, by aportion of the CG situated above the sidewall spacers. Furthermore, thedistance between FGs can be shorter than the feature size, which is thesize allowed by the underlying photolithography technology used.Therefore improved non-volatile memories such as flash memories can bemanufactured with the method of the present invention, using currentlyavailable photolithography technology.

According to an embodiment of the present invention, the floating gateis formed by providing the floating gate on the substrate, the floatinggate having two opposite walls located above the isolation zones, andforming a recess in the isolation zones under the opposite walls of thefloating gate. This may be done by depositing a floating gate layer andforming slits in the floating gate layer, thus forming the oppositewalls of the floating gate.

The step of extending the floating gate may comprise depositing aconductive layer on the opposite walls of the floating gate and on thewalls of the recess in the isolation zones.

The step of depositing a conductive layer on the opposite walls of thefloating gate and on the walls of the recesses in the isolation zonesmay comprise depositing a conductive layer over the floating gate and inthe recesses in the isolation zones, and etching the conductive layer.

The method may further comprise a step of forming a dielectric layer onthe floating gate and on the conductive spacers before forming thecontrol gate.

The method may also comprise a step of providing a tunnel oxide betweenthe semiconductor substrate and the floating gate.

A recess in an isolation zone may be formed by etching.

The step of forming the control gate may comprise the steps ofdepositing a control gate layer, and patterning the control gate layerto form the control gate.

The conductive spacers may be polysilicon spacers.

The present invention also provides a semiconductor device with afloating gate and a control gate. It comprises a substrate with a planarsurface. Two isolation zones are present in the substrate in the planarsurface. A floating gate having two side walls extending vertically withrespect to the planar surface of the substrate is present on thesubstrate between two isolation zones, the walls having a height asmeasured from the planar surface. Conductive spacers extend the floatinggate from each wall laterally with respect to the planar surface, andthey extend vertically with respect to the planar surface at least overthe height of the floating gate side walls. A control gate extendslaterally with respect to the planar surface over the floating gate andthe conductive spacers.

The conductive spacers furthermore extend vertically with respect to theplanar surface over a supplementary height in a recess in the isolationzones. The supplementary height of the conductive spacers increases theeffective coupling of the FG to the CG.

In an array of semiconductor devices according to the present invention,there may be a sub-lithographic slit between floating gates of adjacentsemiconductor devices, i.e. a space in between adjacent floating gateswhich is smaller than the minimal dimensions defined by the lithographicprocess used. This enhances the floating gate to control gate couplingratio.

The present invention also provides a non-volatile memory including asemiconductor device according to the present invention. Thenon-volatile memory may be a flash memory or EEPROM.

FIG. 1 shows a top view of a layout of a plurality of NVM cellsaccording to the prior art, with the CG partly removed.

FIG. 2 shows a cross-section of a prior art NVM cell, according to lineX-X′ in FIG. 1.

FIG. 3 shows a cross-section of a prior art NVM cell, according to lineY-Y′ in FIG. 1.

FIG. 4 is a cross-section of a substrate provided with isolation zones.

FIG. 5 is a cross-section after FG polysilicon and stopping layerdeposition.

FIG. 6 is a cross-section after FG slit etch prior to resist strip.

FIG. 7 is a cross-section of FG slit after resist strip and additionalpolysilicon layer deposition.

FIG. 8 is a cross-section of FG slit after polysilicon spacer etch.Polysilicon spacers form extensions of the FGs.

FIG. 9 is a cross-section of FG slit after IPD and CG polysilicondeposition.

FIG. 10 is a cross-section as in FIG. 9, showing dimensions of differentparts.

FIG. 11 shows a general FG/IPD/CG stack.

FIG. 12 illustrates a detail of FIG. 11, the IPD being formed by adeposited bottom oxide.

FIG. 13 illustrates a detail of FIG. 11, the IPD being formed by afurnace oxidized bottom oxide.

FIG. 14 illustrates a detail of FIG. 11, where the IPD is formed on aspacers extended FG.

FIG. 15 shows a cross-section of a prior art NVM cell after poor FG slitetch (no straight part), according to line Ys-Ys′ in FIG. 1.

FIG. 16 shows a cross-section of a prior art NVM cell after IPD and CGpolysilicon deposition, according to line Ys-Ys′ in FIG. 1.

FIG. 17 shows a cross-section of a prior art NVM cell after CG etch,according to line Ys-Ys′ in FIG. 1.

The present invention will be described with reference to certainembodiments and drawings but the present invention is not limitedthereto but only by the attached claims. The drawings described are onlyschematic and are non-limiting. In the drawings, the size of some of theelements may be exaggerated and not drawn on scale for illustrativepurposes. Where the term “comprising” is used in the present descriptionand claims, it does not exclude other elements or steps. Where anindefinite or definite article is used when referring to a singular noune.g. “a” or “an”, “the”, this includes a plural of that noun unlesssomething else is specifically stated.

According to the present invention, in a first step, a substrate 20 or awell in a substrate is provided. In embodiments of the presentinvention, the term “substrate” may include any underlying material ormaterials that may be used, or upon which a device, a circuit or anepitaxial layer may be formed. In other alternative embodiments, this“substrate” may include a semiconductor substrate such as e.g. a dopedsilicon, a gallium arsenide (GaAs), a gallium arsenide phosphide(GaAsP), a germanium (Ge), or a silicon germanium (SiGe) substrate. The“substrate” may include for example, an insulating layer such as a SiO₂or an Si₃N₄ layer in addition to a semiconductor substrate portion.Thus, the term substrate also includes silicon-on-glass, silicon-onsapphire substrates. The term “substrate” is thus used to definegenerally the elements for layers that underlie a layer or portions ofinterest. Also, the “substrate” may be any other base on which a layeris formed, for example a glass or metal layer. In the followingprocessing will mainly be described with reference to silicon processingbut the skilled person will appreciate that the present invention may beimplemented based on other semiconductor material systems and that theskilled person can select suitable materials as equivalents of thedielectric and conductive materials described below.

As shown in FIG. 4, in the Y-Y′ direction (as defined in FIG. 1), thiswell or substrate 20 has a surface and is provided with shallow trenchisolation (STI) zones 22 or thermally grown field oxide (LOCOS) regions,in order to isolate subsequent (as seen in the Y-Y′ direction) memorycells from each other. Between two STI or LOCOS isolation zones 22, theremaining substrate 20 will form an active area 24.

STI isolation zones 22 may be formed by initially creating a shallowtrench in semiconductor substrate 20, e.g. by a conventionalphotolithographic and anisotropic dry etch process such as a reactiveion etching (RIE) procedure, using e.g. Cl₂ as etchant. The shallowtrench is created to a depth of for example between about 200 to 600 nmin the semiconductor substrate 20. After removal of the photoresistpattern, used for shallow trench definition, by plasma oxygen ashing andcareful wet cleans, a silicon oxide layer is deposited, for example by alow pressure chemical vapor deposition (LPCVD) procedures or by a plasmaenhanced chemical vapor deposition (PECVD) procedure, to a thicknessbetween about 300 to 1500 nm. The shallow trenches are thus completelyfilled. Removal of the silicon oxide from regions other than inside theshallow trenches is accomplished using either a chemical mechanicalpolishing (CMP) procedure, or via a RIE procedure using a suitableetchant, resulting in insulator filled STI regions 22.

If instead of STI zones 22, LOCOS regions are used, they may be formedvia initially forming an oxidation resistant mask, such as siliconnitride, then exposing regions of the semiconductor substrate notprotected by the silicon nitride masking pattern, to a thermal oxidationprocedure. LOCOS regions are thus created at a thickness equal to thedepth of STI regions. After formation of the LOCOS region, the oxidationresistant mask is removed.

STI zones are preferred over LOCOS regions as they can be formed in asmaller dimension than that of the LOCOS regions, which allows thereduction of the cell dimensions, so that cell density can be increased.Therefore, in the following description, only STI zones are furtherconsidered, but it should be understood that the present inventionincludes the process steps described below carried out with LOCOSregions.

As shown in FIG. 5, on top of the substrate 20 provided with STI zones22, a tunnel oxide (Tox) layer 26, comprising silicon dioxide, isformed, preferably by thermally growing it in an oxygen-steam ambient,at a temperature between about 600 to 1000° C., to a thickness betweenabout 6 to 15 nm. Alternatively Rapid Thermal Oxidation (RTO) within-situ steam generation (ISSG) can be used to obtain the tunnel oxidelayer 26.

On top of the tunnel oxide 26, a first polysilicon layer 28 withthickness t_(FG) is deposited, which will later on form the FG. Thedeposition of the first polysilicon layer is preferably done by a CVDprocedure, to a thickness between about 50 to 400 nm. Doping of thepolysilicon layer 28 is either accomplished in situ, during deposition,e.g. via the addition of arsine or phosphine to a silane ambient, or viaan ion implantation procedure, using for example arsenic, phosphorous orboron ions applied to an intrinsic polysilicon layer.

On top of the first polysilicon layer 28, a stopping layer 30 isdeposited, for example consisting of an insulating layer such as SiO₂.

This is shown in FIG. 5. The stopping layer 30 functions as stoppinglayer for a subsequent spacer etching step, and as screening layer forpossible FG implantations.

FG slits 32 are patterned by a common exposure step. A resist layer 34is applied on top of the stopping layer 30 and some parts thereof(depending on the desired pattern) are exposed. Subsequently, thenon-exposed parts (or the exposed parts, depending on the kind of resistused) are washed away, leaving behind a certain pattern of resist,allowing layers not covered by the remaining resist layer to be etchedaway. The etch comprises a breakthrough (BT) step to etch through thestopping layer 30, followed by a polysilicon main etch through the firstpolysilicon layer 28, stopping on the STI 22. Next an oxide etch isperformed forming a recess with depth d in the STI 22. This is shown inFIG. 6. FIG. 6 shows the situation after the oxide etch. The situationrepresented refers to the case with zero etch bias (and thus with edgesperpendicular to the substrate surface). The etch bias is defined by:etch bias=L _(—) CD−E _(—) CD.Before removing the remainder of the resist layer 34, possible polymersand native oxide is removed from the FG sidewalls 36. Next the resist 34is removed, e.g. via plasma oxygen ashing and careful wet cleans,leaving behind the stopping layer 30.

Preferably in a time critical sequence avoiding re-oxidation of FGsidewalls 36, succeeding a pre-clean, an additional polysilicon layer 38with thickness t_(SP) is deposited, as shown in FIG. 7, over thestopping layer 30 and in the slit 32. Preferably the polysilicon layer38 is in-situ doped with the same dopant as the first polysilicon layer28.

Thereafter, polysilicon spacers 40 are anisotropically etched, using thestopping layer 30 and STI 22 for end point detection of the main etch.The polysilicon spacers 40 will function as extensions of the FGs, thusnarrowing the FG slit 32, as shown in FIG. 8. The dimensions L_CD, etchbias, E_CD and t_(SP) determine the final critical dimensions (CD) ofthe slit (FGS_CD):E _(—) CD=L _(—) CD−etch biasFGS _(—) CD=E _(—) CD−2*t _(SP) =L _(—) CD−etch bias−2*t _(SP)After removing the stopping layer 30, an interpoly dielectric (IPD) 42is formed, see FIG. 9. The IPD 42 preferably comprises a plurality ofinsulating materials, e.g. an Oxide Nitride Oxide (ONO) layer, and maybe formed or grown by conventional techniques. An ONO layer preferablycomprises successive layers of silicon dioxide, silicon nitride andsilicon dioxide. The total dielectric thickness of the ONO layergenerally is between about 10 to 50 nm.

After forming the IPD layer 42, CG polysilicon 44 is deposited(preferably in situ doped), as shown in FIG. 9. The deposition of the CGpolysilicon layer 44 may be done by LPCVD procedures, to a thicknessbetween about 50 to 400 nm. Doping of the CG polysilicon layer 44 iseither accomplished in situ, during deposition, via the addition of asuitable dopant impurity such as arsine or phosphine to a silaneambient, or via an ion implantation procedure, using such a dopant, e.g.arsenic, phosphorous or boron ions applied to an intrinsicallypolysilicon layer.

In a last step in the formation of a NVM according to the presentinvention, CGs are etched (not shown in the drawings).

Cell formation is finalized with processing as known by a person skilledin the art (e.g. source/drain formation, salicidation, etc.).

Preferably, the following parameters are optimized when implementingspacers 40 for extending FGs in a process according to the presentinvention:

-   -   FG thickness t_(FG): the larger the FG thickness t_(FG) (i.e.        the higher the FG), the more overlap area between FG and CG is        created, and thus the larger the capacitance C_(FC) between FG        and CG will be.    -   L_CD: the smaller L_CD, the smaller the width of the slit 32,        the higher the FG to CG coupling ratio. L_CD is limited by        photo-lithographic means.    -   E_CD: The larger E_CD, i.e. the more the bottom part of the FG        is etched straight, the less fence leakage will occur. Remaining        fences, consisting of IPD (e.g. ONO), occur due to the IPD        deposition after etching slits in the FG polysilicon and        succeeding CG patterning. When the profile of the slits 60        etched in the first polysilicon layer 62 is sloped or shows        irregularities (as shown in FIG. 15), then after IPD 64        formation and CG polysilicon 66 deposition (as shown in FIG.        16), IPD fences will mask the first polysilicon layer 62 during        CG patterning. This causes polysilicon residues 68 next to the        IPD fences 70, as shown in FIG. 17. These residues 68        short-circuit the FGs, causing leakage and lowering the circuit        yield. Fence leakage can be prevented by etching the bottom part        of the FG extremely straight and perpendicular at the STI zone        (>85° angle with STI).    -   Thickness of the additional polysilicon layer for forming the        spacer, t_(SP): the thicker the polysilicon layer forming the        spacers 40, the smaller the width of the slit 32, and the higher        the FG to CG coupling ratio.    -   Depth d of the recess: the deeper the recess, the larger the FG        to CG overlap area can be.

The height of the straight part of the FG is important as it determinesthe risk of fence leakage. The height of the straight part of the FG(perpendicular at STI) equals (see FIG. 10):t_(FG)−t_(SP)+d

The spacers extended FG approach of the present invention has thefollowing advantages:

-   -   It is well compatible with common (embedded) NVM processes. No        additional masks are required.    -   A high packing density is feasible due to deep sub-micron slits        (thus a small FG to FG distance) without reducing the litho and        etch process window. Slit sizes are smaller than possible with        currently available lithographic processes.    -   High FG to CG coupling ratios are feasible due to small slits        (small FG to FG distance).    -   Electric fields over the IPD 42 are considerably lower for a        spacers extended FG approach of the present invention than for        prior art devices, as no sharp edges occur where field lines are        dense. This is illustrated in FIGS. 11 to 14. The circle 50 in        FIG. 11 (corresponding to the circle 50 in FIG. 9) indicates        which FG edge is considered in a FG/IPD/CG stack, and FIG. 12 to        FIG. 14 show different possibilities for FG edges. FIG. 12        illustrates an IPD layer 52 in case the bottom oxide layer is        deposited. There is a perfect step coverage, but there are sharp        FG edges causing field enhancement. FIG. 13 shows an IPD layer        54 in case the bottom oxide is furnace oxidized. In this case,        sharpening strongly depends on the oxidation conditions        (temperature, time, ambient): dry is bad, wet is worse and rapid        thermal oxidation (RTO) is best. FIG. 14 shows an oxide layer 42        in case of a spacers extended FG according to the present        invention. This solution enhances reliability of the IPD 42        (breakdown probability is less) and data retention of the NVMs.        Applying a spacers extended FG approach according to the present        invention prevents IPD sharpening/thinning at the FG edges in        case that part of the IPD is grown in a furnace.    -   Fence leakage (leakage from FG to FG via residues next to ONO        fences) can be completely prevented, thus causing a high yield.    -   When applying manufacturable photo and etch processes, the final        critical dimension of the FG slit 32 is determined by the        thickness of a polysilicon layer 38 and is therefore very        accurately controlled. Etching the polysilicon spacer 40 using        an end point system is manufacturable. The control of the        critical dimension of the deep sub-micron FG slits 32 is        therefore no longer dependent on the FG slit photo and etch        process but mainly depends on the control of the thickness of        the polysilicon layer 38.

1. Method for manufacturing on a substrate a semiconductor device with afloating-gate and a control-gate, comprising the steps of: first formingisolation zones in the substrate, thereafter forming a floating gate onthe substrate between two isolation zones, thereafter extending thefloating gate using conductive spacers, and thereafter forming a controlgate over the floating gate and the conductive spacers.
 2. Methodaccording to claim 1, wherein the step of forming the floating gatecomprises: providing the floating gate on the substrate, the floatinggate having two opposite walls located above the isolation zones,forming a recess in the isolation zones under the opposite walls of thefloating gate.
 3. Method according to claim 2, wherein the step ofproviding the floating gate, comprises: depositing a floating gate layerforming slits in the floating gate layer, thus forming the oppositewalls of the floating gate.
 4. Method according to claim 2, wherein thestep of extending the floating gate comprises depositing a conductivelayer on the opposite walls of the floating gate and on the walls of therecess in the isolation zones.
 5. Method according to claim 4, whereinthe step of depositing a conductive layer on the opposite walls of thefloating gate and on the walls of the recesses in the isolation zonescomprises: depositing a conductive layer over the floating gate and inthe recesses in the isolation zones etching the conductive layer. 6.Method according to claim 1, further comprising a step of forming adielectric layer on the floating gate and on the conductive spacersbefore forming the control gate.
 7. Method according to claim 1, whereinthe isolation zones are shallow trench isolation (STI) zones.
 8. Methodaccording to claim 1, wherein the isolation zones are LOCOS regions. 9.Method according to claim 2, wherein a recess in an isolation zone isformed by etching.
 10. Method according to claim 1, comprising the stepof providing a tunnel oxide between the semiconductor substrate and thefloating gate.
 11. Method according to claim 1, wherein the step offorming the control gate comprises: depositing a control gate layer, andpatterning the control gate layer to form the control gate.
 12. Methodaccording to claim 1, wherein the conductive spacers are polysiliconspacers.
 13. Semiconductor device with a floating-gate to control-gatecoupling ratio, comprising: a substrate with a planar surface, twoisolation zones in the substrate in the planar surface, a floating gateon the substrate between two isolation zones, the floating gate havingtwo side walls extending vertically with respect to the planar surfaceof the substrate, the walls having a height as measured from the planarsurface, conductive spacers extending the floating gate from each walllaterally with respect to the planar surface, the conductive spacersextending vertically with respect to the planar surface at least overthe height of the floating gate side walls, and a control gate extendinglaterally with respect to the planar surface over the floating gate andthe conductive spacers.
 14. Semiconductor device according to claim 13,wherein the conductive spacers furthermore extend vertically withrespect to the planar surface over a supplementary height in a recessbelow the surface.
 15. An array of semiconductor devices of claim 13,wherein there is a sub-lithographic slit between floating gates ofadjacent semiconductor devices.
 16. A non-volatile memory including thesemiconductor device according to claim
 13. 17. The non-volatile memoryaccording to claim 16, wherein the memory is a flash memory.
 18. Thenon-volatile memory according to claim 16, wherein the memory is anEEPROM.